1. Field of the Invention
The present invention relates to a frame transfer method and device, and in particular to a frame transfer method and device in an L2 switch using a shared buffer.
2. Description of the Related Art
Recently, devices have been micromachined, and an operation speed within a device and an interface speed between devices have been enhanced, so that a malfunction within the device, a noise of the interface between the devices, and the like have become considerable. Therefore, an abnormal operation may sometimes occur in an L2 switch or the like upon managing a shared buffer.
While such a problem has been approached by correction of data with an error correction code (ECC) or the like, the correction can be performed only to data with a single bit error or the like, but could not be performed to data with plural bit errors.
Therefore, when a parity error, an ECC error (uncorrectable error upon detecting plural bit errors), and the like are detected in a circuit managing the shared buffer, the prior art has prevented a malfunction by invalidating an area of the shared buffer. The prior art will now be described referring to the attached figures.
FIG. 7 schematically shows an example of the L2 switch using the shared buffer which has been conventionally known. As for L2 frame data (hereinafter, occasionally referred to as simply frame) inputted from each of ports P0-P3 of line interface unit (LIU) cards C#0-C#3, L2 frame terminating/generating portions TG#0-TG#3 respectively retrieve forwarding database (FDB) by using a destination address (DA) within the frame to acquire card information and port information of a frame transfer destination from the database FDB, and transfer the frame to a switch card SWC side. Upon the transferring, the card information and the port information are added to the frame.
When the destination address within the frame is not registered in the database FDB, the L2 frame terminating/generating portions TG#0-TG#3 add the card information and the port information to the frame to be transferred (flooded) to all of the LIU cards C#0-C#3, since the card information and the port information are not added to the L2 frame inputted from the switch card SWC. Namely, in the interface between the LIU cards C#0-C#3 and the switch card SWC, the card information and the port information are added for the purpose of transferring within the device.
The switch card SWC multiplexes the frames (including card information and port information) received through the ports P0-P3 from each of the LIU cards C#0-C#3 to be once stored in the shared buffer SB. Also, the address of the shared buffer SB upon storing the frame in the shared buffer SB is stored in a queue which will be described later, provided and managed per LIU card as a destination and per priority degree (hereinafter, referred to simply as priority) within the LIU card. Upon reading from the shared buffer SB, a switch portion SP performs a priority control per LIU card to acquire the address from the queue. The data (frame) is read from the shared buffer SB by using the acquired address to be transferred to the object LIU card.
The LIU cards C#0-C#3 specify a transfer destination port (any one or more ports of P0-P3 of LIU card) based on the L2 frame (including card information and port information) having received from the switch card SWC, and transfers the frame to the associated port. At this time, the information added to the frame in the L2 switch SW is deleted.
The specific arrangement and operation of the prior art switch card SWC in the L2 switch SW will now be described referring to FIGS. 8-11.
FIG. 8 shows a prior art example of the switch portion SP composing the switch card SWC together with the shared buffer SB. Firstly, upon writing a frame to the shared buffer SB, a frame inputted from each of the ports P0-P3 of the switch portion SP shown in FIG. 7 is multiplexed by a frame multiplexer 1 and transferred to a WAF read controller 2, a parity generator 3, a destination information/priority control information extractor 4, and the shared buffer SB.
The destination information/priority control information extractor 4 extracts destination information and priority control information added to the frame in the L2 frame terminating/generating portions TG#0-TG#3 in the LIU cards C#0-C#3, and transfers the extracted information to a write controller 6. Concurrently, the WAF read controller 2 acquires a free area (address) of the shared buffer SB from a Fifo (WAF: Write Address Fifo) 5 by designating a circular (iteration) address. Also, the WAF read controller 2 transfers the acquired free address to the shared buffer SB and the write controller 6 as a “write address”. The parity generator 3 outputs a result (parity bit) after performing a parity calculation for the detection of failure to the frame inputted and outputs the frame, so that the shared buffer SB stores the parity result and the frame in the free area (write address) acquired from the write address Fifo 5 through the WAF read controller 2.
At this time, the write controller 6 sequentially selects the LIU card as a destination and a concerned queue among read queues 8_1-8_4 (hereinafter, occasionally represented by a reference numeral 8) provided per priority of the LIU card, based on the destination information and the priority control information transferred from the destination information/priority control information extractor 4, and transfers the write address acquired from the write address Fifo 5 to the selected queue. Also, a write flag WFLG for the selected queue is transferred to the read controller 10.
It is to be noted that four units of read queues 8 are shown in the example of FIG. 8, which indicates that e.g. the read queue 8-4 of destination α—high priority and the read queue 8-2 of destination α—low priority correspond to the LIU card C#1, and the read queue 8-3 of destination β—high priority and the read queue 8-1 of destination β—low priority correspond to the LIU card C#2. Accordingly, in the presence of four units of LIU cards C#0-C#3 as shown in the example of FIG. 7, 8 units of read queues are required, where only four units of the read queues are shown for convenience sake.
The parity generator among parity generators 7_1-7_4 (hereinafter, occasionally represented by a reference numeral 7) corresponding to the selected queue 8 outputs a result (parity bit) after performing the parity calculation for the detection of failure to the write address transferred from the write controller 6 and the write address, and the concerned queue 8 stores the write address as a “read address”. When receiving the write flag WFLG transferred from the write controller 6, the read controller 10 monitors a queue capacity (read address) per queue 8, and counts up a capacity counter (not shown) installed in the read controller 10.
Upon reading the frame from the shared buffer SB, the read controller 10 can determine whether or not the frame data to be outputted is accumulated within the shared buffer SB, as mentioned above, with the capacity counter indicating the capacity of the read address stored in each queue 8.
When the capacity counter for monitoring per queue 8 is not “0”, the read controller 10 performs the priority control and a fairness control (e.g. round robin) of each queue 8, and reads the read address from the queue 8 selected as a result of the control. Parity checkers 9_1-9_4 (hereinafter, occasionally represented by a reference numeral 9) perform the parity calculation to the read address read to be compared with the parity bit assigned by the parity generator 7.
In the presence of error found as a result of the comparison, the read controller 10 receives an error signal, and discards the read address read from the queue 8, so that the transfer to the shared buffer SB is not performed. Namely, the frame corresponding to the concerned read address is not read from the shared buffer. In the absence of error, the read controller 10 transfers the read address read from the queue 8 to the shared buffer SB and a WAF write controller 11. Also, the read controller 10 transfers to a frame demultiplexer 14 the information of the selected queue as output port information. When the destination α corresponds to the LIU card C#1 as with the above-mentioned example, information P1 indicating the port P1 of the switch portion SP corresponding to the output to the LIU card C#1 is transferred to the frame demultiplexer 14 as output port information.
The shared buffer SB takes out the data (frame) based on the read address received from the read controller 10, and the parity checker 12 at the subsequent stage performs the parity calculation to the data to be compared with the parity bit assigned by the parity generator 3.
In the presence of error found as a result of the comparison, the read frame is discarded by a data discard determining portion 13. In the absence of error, the read frame is transferred to the frame demultiplexer 14. The frame demultiplexer 14 demultiplexes the frame received from the data discard determining portion 13 to be transferred to a port designated by the output port information received from the read controller 10.
Also, the WAF write controller 11 stores the read address received from the read controller 10 in the write address Fifo 5 as data. The then address of the write address Fifo 5 assumes a circular address managed by the WAF write controller 11. By this operation, the shared buffer address where the frame is read from the shared buffer SB is to be stored in the write address Fifo 5 as a free address. In the following description, this operation is occasionally described as “returning a free address or return of a free address”.
The above-mentioned write/read operation will now be described referring to the attached figures as an operation up to transferring the frame data inputted from each of the ports P0-P3 in the switch card SWC shown in FIG. 8 to the ports P0-P3 which form the destination.
Firstly, in the frame write side operation (writing operation) in the shared buffer SB having areas of addresses “0-1023” shown in FIG. 9, destinations and priorities are stored in header information head1-head4 of input frame data A, B, C, and D. As shown in FIG. 8, it is supposed that destination β—low priority, destination α—low priority, destination β—high priority, and destination β—high priority are respectively added to the frame data. It is to be noted that FIG. 9 shows an example where frame data with the same destination and different priorities are inputted at different times.
The frame data inputted from the ports P0-P3 respectively corresponding to the LIU cards C#0-C#3 are multiplexed by the frame multiplexer 1.
Thereafter, the WAF read controller 2 requests the write address Fifo 5 to acquire an address for storing the frame data in the shared buffer SB per frame data (in this example, the write addresses “0, 1, 2, and 3” for the shared buffer SB are acquired as a result).
Specifically, when receiving the frame data A, the WAF read controller 2 transmits the address “0” to the write address Fifo 5 (WAF) 5 as e.g. an initial value. The write address Fifo 5 transmits a free address “0” of the shared buffer SB to the WAF read controller 2 as data (subsequent address for the shared buffer SB). Similarly, when receiving the frame data B, C, and D, the WAF read controller 2 transmits circular addresses “1”, “2”, and “3” respectively to the write address Fifo 5, which sequentially transmits data “1”, “2”, and “3” of the circular addresses to the WAF read controller 2.
Thus, the WAF read controller 2, every time the frame data is received, increments an address to be transmitted to the write address Fifo 5, thereby requesting an acquisition of the shared buffer storing address (at steps S1 and S2). The WAF read controller 2 sequentially acquires the free addresses (addresses “0, 1, 2, and 3” in this example) of the shared buffer SB from the write address Fifo 5 (at step S3).
The parity generator 3 adds parity bits for the detection of failure to the acquired free address spaces “0, 1, 2, and 3” (at step S5), and writes the frame data A-D respectively in the addresses “0, 1, 2, and 3” of the shared buffer SB (at step S4).
Also, the destination information/priority control information extractor 4 extracts the header information of the frame data (in this example, destination β—low priority, destination α—low priority, destination β—high priority, and destination α—high priority corresponding to the frame data A, B, C, D respectively). The write controller 6, based on the extracted header information, writes in any one of the read queues 8_1-8_4 which are the transferring destination, the write address acquired from the WAF read controller 2 as data of the read address with the parity bit for the detection of failure generated by the parity generators 7_1-7_4 added (at step S5). In this example, the addresses “0, 1, 2, and 3” are respectively written as read addresses in the queues 8_1-8_4 corresponding to the write addresses “0, 1, 2, and 3”.
In the read side operation (reading operation) at normal time shown in FIG. 10, the read controller 10 performs read scheduling (arbitration) to the read queues 8_1-8_4 in which the write addresses are stored in FIG. 9 (at step S6), and acquires the read addresses from the read queues 8_1-8_4. Upon the acquiring, checking the parity bit for the detection of failure is performed by the parity checkers 9_1-9_4 (at step S7). The addresses (no error is detected in failure detection) acquired at this time are used as addresses for reading the frame data from the shared buffer SB. It is to be noted that since the scheduling is performed in order of destination α with high priority, destination β with high priority, destination α with low priority, and destination β with low priority in this example, the addresses (read addresses) of the shared buffer SB are sequentially read in order of read queues 8-4, 8-3, 8-2, and 8-1, and accordingly from the shared buffer SB, the frame data D, C, B, and A respectively corresponding to order of addresses “3, 2, 1, and 0” are read.
The read controller 10 returns the acquired addresses (no error is detected in the failure detection) to the write address Fifo 5 as free addresses after reading the frame from the shared buffer SB (at steps S8 and S9), thereby releasing an available area. In this example, the next address data “3, 2, 1, and 0” are stored in the addresses “0, 1, 2, and 3” of the write address Fifo 5 through the WAF write controller 11 in order of reading the frame data D, C, B, and A from the shared buffer SB.
Accordingly, when the addresses “0, 1, 2, and 3” of the write address Fifo 5 are designated from the WAF read controller 2, writing the frame is performed respectively to the free addresses “3, 2, 1, and 0” of the shared buffer SB. However, since the WAF read controller 2 designates the circular address up to “1023” for the write address Fifo 5, when the WAF address “3” is designated corresponding to the frame data D as mentioned above, the address “4” of the write address Fifo 5 is to be designated for the frame which arrives next.
In the reading operation example (abnormal time) shown in FIG. 11, as with FIG. 10, read scheduling (arbitration) is performed by the read controller 10 to the read queues 8_1-8_4 in which the write addresses are stored as shown in FIG. 9 (at step S6) to acquire the read address from the read queue 8. Upon the acquiring, checking the parity bit for the detection of failure is performed (at step S7). The example of FIG. 11 shows a case where an error Err occurs in the parity check for the detection of failure in a part (addresses “1 and 2”) of the addresses acquired. As for the addresses without error, the operation is the same as that described in FIG. 10.
As to data (addresses of the shared buffer SB) where the error Err has occurred, it is considered that a bit error has occurred. Therefore, the data (addresses) read from the queue 8 are invalidated (at step S10), and the addresses are not used for reading the frame data from the shared buffer SB (at step S11).
At this time, the read controller 10 does not return the addresses (errors are detected upon the failure detection) acquired to the write address Fifo 5 as areas read from the shared buffer SB. Specifically, the read controller 10 does not notify the data (addresses) having the errors Err occurred to the WAF write controller 11. Accordingly, in this example, only the frame data D and A of the addresses “3 and 0”, free from error, of the shared buffer SB are read, and concurrently only the addresses “3 and 0” of the shared buffer SB are sequentially written as data of the addresses “0 and 1” of the write address Fifo 5. However, the data of addresses “2 and 3” of the write address Fifo 5 remain the same as FIG. 9.
Thus, in the prior art example, when an abnormal operation has occurred in the management of the shared buffer, a shared buffer area portion corresponding thereto is invalidated (not read), so that a malfunction has been prevented.
It is to be noted that there has been proposed a memory monitoring method which is provided with a used map monitoring portion, an unused map monitoring portion, and a search monitoring portion in addition to a data storing memory, an address storing memory, a parity inserting portion of a free address storing memory, and a parity abnormality detector, and which detects an address composition, an address disappearance, and an abnormal chain occurrence per chain (see e.g. patent document 1).
Also, there has been proposed a device in which an address management circuit portion of a shared buffer has a CAM managing a free address of the shared buffer and a read address per output port No., and an address retrieving portion retrieving the free address and the read address from the CAM, a management method of the address has a step of accumulating the free address of the shared buffer and the read address in a single CAM, and a step of retrieving the free address or the read address of the shared buffer by an address pointer of the CAM, and the address of the shared buffer of an ATM cell is managed (see e.g. patent document 2).
[Patent document 1] Japanese patent application laid-open No. 11-102325
[Patent document 2] Japanese patent application laid-open No. 11-261569
The operation description of the prior art examples shown in FIGS. 8-11 mentions the examples of no bit error occurrence (FIG. 10) and the bit error occurrence (FIG. 11) in the addresses read from the read queues 8_1-8_4, in which the read controller 10 has read all of the addresses written in the read queue 8 after the schedule management, where there is a difference in the state of the write address Fifo 5 after reading all of the addresses between the case where an error has occurred and the case where no error has occurred.
When no error has occurred, the frame data is read from the shared buffer SB by using the data (address) read from the read queue 8, thereby returning the data (address of the shared buffer SB) to the write address Fifo 5 as a free address space within the shared buffer SB. In this example, the writing in the read queue 8 and the read from the read queue 8 are respectively performed four times, and the return of free address to the write address Fifo 5 is performed four times (writing is performed four times), so that the number of free address spaces of the shared buffer SB stored in the write address Fifo 5 assumes 1024.
On the other hand, when an error has occurred, there is a high possibility that the data (address) read upon error occurrence includes a bit error. Therefore, the read data is invalidated, and the return of free address to the write address Fifo 5 is not performed. For this reason, in this example, the writing in the read queue 8 and the reading from the read queue 8 are respectively performed four times, and the return to the write address Fifo 5 is performed two times (write is performed two times), so that the number of free address spaces stored in the write address Fifo 5 assumes 1022 (−2 compared with the case of no error occurrence). Namely, when the read address is not returned as a free address to the write address Fifo 5, the addresses “1 and 2” of the shared buffer SB remain unused.
This results from the fact that the free area management of the write address Fifo 5 is performed based on a memory capacity. Namely, in the state of FIG. 11, the free addresses “0 and 3” of the shared buffer SB are stored in the addresses “1 and 0” of the write address Fifo 5, and the invalid (unused) addresses “2 and 3” of the shared buffer SB are stored in the addresses “2 and 3”. The then free address areas (free address areas of the shared buffer SB) of the write address Fifo 5 are “1024−2=1022”. In this state, the next frame data is written in the shared buffer SB with the data “4” indicated in the address “4” of the write address Fifo 5 being made a write address. The writing in the shared buffer SB is performed up to the address “1023” by the circular address, and then is performed to the addresses “0 and 1”.
At this time, the capacity of the write address Fifo 5 becomes full (free address area of the shared buffer SB is 0), so that the writing in the shared buffer SB is stopped by the WAF read controller 2 managing the write address Fifo 5. Thereafter, when any of frame data is read from the shared buffer SB, the address of the shared buffer SB from which the frame data is read is returned as a free address to the address “2” of the write address Fifo 5.
As a result, the frame data B and C remain left in the shared buffer SB without being read.
Thus, the address space of the shared buffer SB in which an error was once detected and which could not be returned to the write address Fifo 5 can not be returned in the subsequent operation. Therefore, physically existing 1024 address spaces are reduced to 1022 (−2) address spaces by the error, so that there has been a problem that the capacity of the shared buffer SB becomes smaller every time an error occurs.